core/stdarch/crates/core_arch/src/loongarch32/
mod.rs

1//! `LoongArch32` intrinsics
2
3use crate::arch::asm;
4
5#[allow(improper_ctypes)]
6unsafe extern "unadjusted" {
7    #[link_name = "llvm.loongarch.cacop.w"]
8    fn __cacop(a: i32, b: i32, c: i32);
9    #[link_name = "llvm.loongarch.csrrd.w"]
10    fn __csrrd(a: i32) -> i32;
11    #[link_name = "llvm.loongarch.csrwr.w"]
12    fn __csrwr(a: i32, b: i32) -> i32;
13    #[link_name = "llvm.loongarch.csrxchg.w"]
14    fn __csrxchg(a: i32, b: i32, c: i32) -> i32;
15}
16
17/// Generates the cache operation instruction
18#[inline]
19#[unstable(feature = "stdarch_loongarch", issue = "117427")]
20pub unsafe fn cacop<const IMM12: i32>(a: i32, b: i32) {
21    static_assert_simm_bits!(IMM12, 12);
22    __cacop(a, b, IMM12);
23}
24
25/// Reads the CSR
26#[inline]
27#[unstable(feature = "stdarch_loongarch", issue = "117427")]
28pub unsafe fn csrrd<const IMM14: i32>() -> i32 {
29    static_assert_uimm_bits!(IMM14, 14);
30    __csrrd(IMM14)
31}
32
33/// Writes the CSR
34#[inline]
35#[unstable(feature = "stdarch_loongarch", issue = "117427")]
36pub unsafe fn csrwr<const IMM14: i32>(a: i32) -> i32 {
37    static_assert_uimm_bits!(IMM14, 14);
38    __csrwr(a, IMM14)
39}
40
41/// Exchanges the CSR
42#[inline]
43#[unstable(feature = "stdarch_loongarch", issue = "117427")]
44pub unsafe fn csrxchg<const IMM14: i32>(a: i32, b: i32) -> i32 {
45    static_assert_uimm_bits!(IMM14, 14);
46    __csrxchg(a, b, IMM14)
47}