core/stdarch/crates/core_arch/src/loongarch32/
mod.rs

1//! `LoongArch32` intrinsics
2
3use crate::arch::asm;
4
5#[allow(improper_ctypes)]
6unsafe extern "unadjusted" {
7    #[link_name = "llvm.loongarch.cacop.w"]
8    fn __cacop(a: i32, b: i32, c: i32);
9    #[link_name = "llvm.loongarch.csrrd.w"]
10    fn __csrrd(a: i32) -> i32;
11    #[link_name = "llvm.loongarch.csrwr.w"]
12    fn __csrwr(a: i32, b: i32) -> i32;
13    #[link_name = "llvm.loongarch.csrxchg.w"]
14    fn __csrxchg(a: i32, b: i32, c: i32) -> i32;
15}
16
17/// Generates the cache operation instruction
18#[inline]
19#[unstable(feature = "stdarch_loongarch", issue = "117427")]
20pub unsafe fn cacop<const IMM5: i32, const IMM_S12: i32>(b: i32) {
21    static_assert_uimm_bits!(IMM5, 5);
22    static_assert_simm_bits!(IMM_S12, 12);
23    __cacop(IMM5, b, IMM_S12);
24}
25
26/// Reads the CSR
27#[inline]
28#[unstable(feature = "stdarch_loongarch", issue = "117427")]
29pub unsafe fn csrrd<const IMM14: i32>() -> i32 {
30    static_assert_uimm_bits!(IMM14, 14);
31    __csrrd(IMM14)
32}
33
34/// Writes the CSR
35#[inline]
36#[unstable(feature = "stdarch_loongarch", issue = "117427")]
37pub unsafe fn csrwr<const IMM14: i32>(a: i32) -> i32 {
38    static_assert_uimm_bits!(IMM14, 14);
39    __csrwr(a, IMM14)
40}
41
42/// Exchanges the CSR
43#[inline]
44#[unstable(feature = "stdarch_loongarch", issue = "117427")]
45pub unsafe fn csrxchg<const IMM14: i32>(a: i32, b: i32) -> i32 {
46    static_assert_uimm_bits!(IMM14, 14);
47    __csrxchg(a, b, IMM14)
48}
core/stdarch/crates/core_arch/src/loongarch32/mod.rs

core/stdarch/crates/core_arch/src/loongarch32/
mod.rs
