asm_experimental_arch

The tracking issue for this feature is: #93335

This feature tracks asm! and global_asm! support for the following architectures:

  • NVPTX
  • PowerPC
  • Hexagon
  • MIPS32r2 and MIPS64r2
  • wasm32
  • BPF
  • SPIR-V
  • AVR
  • MSP430
  • M68k
  • CSKY
  • SPARC

Register classes

ArchitectureRegister classRegistersLLVM constraint code
MIPSreg$[2-25]r
MIPSfreg$f[0-31]f
NVPTXreg16None*h
NVPTXreg32None*r
NVPTXreg64None*l
Hexagonregr[0-28]r
PowerPCregr0, r[3-12], r[14-28]r
PowerPCreg_nonzeror[3-12], r[14-28]b
PowerPCfregf[0-31]f
PowerPCvregv[0-31]Only clobbers
PowerPCcrcr[0-7], crOnly clobbers
PowerPCxerxerOnly clobbers
wasm32localNone*r
BPFregr[0-10]r
BPFwregw[0-10]w
AVRregr[2-25], XH, XL, ZH, ZLr
AVRreg_upperr[16-25], XH, XL, ZH, ZLd
AVRreg_pairr3r2 .. r25r24, X, Zr
AVRreg_iwr25r24, X, Zw
AVRreg_ptrX, Ze
MSP430regr[0-15]r
M68kregd[0-7], a[0-7]r
M68kreg_datad[0-7]d
M68kreg_addra[0-3]a
CSKYregr[0-31]r
CSKYfregf[0-31]f
SPARCregr[2-29]r
SPARCyregyOnly clobbers

Notes:

  • NVPTX doesn't have a fixed register set, so named registers are not supported.

  • WebAssembly doesn't have registers, so named registers are not supported.

Register class supported types

ArchitectureRegister classTarget featureAllowed types
MIPS32regNonei8, i16, i32, f32
MIPS32fregNonef32, f64
MIPS64regNonei8, i16, i32, i64, f32, f64
MIPS64fregNonef32, f64
NVPTXreg16Nonei8, i16
NVPTXreg32Nonei8, i16, i32, f32
NVPTXreg64Nonei8, i16, i32, f32, i64, f64
HexagonregNonei8, i16, i32, f32
PowerPCregNonei8, i16, i32, i64 (powerpc64 only)
PowerPCreg_nonzeroNonei8, i16, i32, i64 (powerpc64 only)
PowerPCfregNonef32, f64
PowerPCvregN/AOnly clobbers
PowerPCcrN/AOnly clobbers
PowerPCxerN/AOnly clobbers
wasm32localNonei8 i16 i32 i64 f32 f64
BPFregNonei8 i16 i32 i64
BPFwregalu32i8 i16 i32
AVRreg, reg_upperNonei8
AVRreg_pair, reg_iw, reg_ptrNonei16
MSP430regNonei8, i16
M68kreg, reg_addrNonei16, i32
M68kreg_dataNonei8, i16, i32
CSKYregNonei8, i16, i32
CSKYfregNonef32,
SPARCregNonei8, i16, i32, i64 (SPARC64 only)
SPARCyregN/AOnly clobbers

Register aliases

ArchitectureBase registerAliases
Hexagonr29sp
Hexagonr30fr
Hexagonr31lr
PowerPCr1sp
PowerPCr31fp
PowerPCr[0-31][0-31]
PowerPCf[0-31]fr[0-31]
BPFr[0-10]w[0-10]
AVRXHr27
AVRXLr26
AVRZHr31
AVRZLr30
MSP430r0pc
MSP430r1sp
MSP430r2sr
MSP430r3cg
MSP430r4fp
M68ka5bp
M68ka6fp
M68ka7sp, usp, ssp, isp
CSKYr[0-3]a[0-3]
CSKYr[4-11]l[0-7]
CSKYr[12-13]t[0-1]
CSKYr14sp
CSKYr15lr
CSKYr[16-17]l[8-9]
CSKYr[18-25]t[2-9]
CSKYr28rgb
CSKYr29rtb
CSKYr30svbr
CSKYr31tls
SPARCr[0-7]g[0-7]
SPARCr[8-15]o[0-7]
SPARCr[16-23]l[0-7]
SPARCr[24-31]i[0-7]

Notes:

  • TI does not mandate a frame pointer for MSP430, but toolchains are allowed to use one; LLVM uses r4.

Unsupported registers

ArchitectureUnsupported registerReason
Allsp, r14/o6 (SPARC)The stack pointer must be restored to its original value at the end of an asm code block.
Allfr (Hexagon), fp (PowerPC), $fp (MIPS), Y (AVR), r4 (MSP430), a6 (M68k), r30/i6 (SPARC)The frame pointer cannot be used as an input or output.
Allr19 (Hexagon), r29 (PowerPC), r30 (PowerPC)These are used internally by LLVM as "base pointer" for functions with complex stack frames.
MIPS$0 or $zeroThis is a constant zero register which can't be modified.
MIPS$1 or $atReserved for assembler.
MIPS$26/$k0, $27/$k1OS-reserved registers.
MIPS$28/$gpGlobal pointer cannot be used as inputs or outputs.
MIPS$raReturn address cannot be used as inputs or outputs.
HexagonlrThis is the link register which cannot be used as an input or output.
PowerPCr2, r13These are system reserved registers.
PowerPClrThe link register cannot be used as an input or output.
PowerPCctrThe counter register cannot be used as an input or output.
PowerPCvrsaveThe vrsave register cannot be used as an input or output.
AVRr0, r1, r1r0Due to an issue in LLVM, the r0 and r1 registers cannot be used as inputs or outputs. If modified, they must be restored to their original values before the end of the block.
MSP430r0, r2, r3These are the program counter, status register, and constant generator respectively. Neither the status register nor constant generator can be written to.
M68ka4, a5Used internally by LLVM for the base pointer and global base pointer.
CSKYr7, r28Used internally by LLVM for the base pointer and global base pointer.
CSKYr8Used internally by LLVM for the frame pointer.
CSKYr14Used internally by LLVM for the stack pointer.
CSKYr15This is the link register.
CSKYr[26-30]Reserved by its ABI.
CSKYr31This is the TLS register.
SPARCr0/g0This is always zero and cannot be used as inputs or outputs.
SPARCr1/g1Used internally by LLVM.
SPARCr5/g5Reserved for system. (SPARC32 only)
SPARCr6/g6, r7/g7Reserved for system.
SPARCr31/i7Return address cannot be used as inputs or outputs.

Template modifiers

ArchitectureRegister classModifierExample outputLLVM modifier
MIPSregNone$2None
MIPSfregNone$f0None
NVPTXreg16Noners0None
NVPTXreg32Noner0None
NVPTXreg64Nonerd0None
HexagonregNoner0None
PowerPCregNone0None
PowerPCreg_nonzeroNone3None
PowerPCfregNone0None
SPARCregNone%o0None
CSKYregNoner0None
CSKYfregNonef0None

Flags covered by preserves_flags

These flags registers must be restored upon exiting the asm block if the preserves_flags option is set:

  • AVR
    • The status register SREG.
  • MSP430
    • The status register r2.
  • M68k
    • The condition code register ccr.
  • SPARC
    • Integer condition codes (icc and xcc)
    • Floating-point condition codes (fcc[0-3])