13. Armv7-R bare-metal (hard-float)¶

The armv7r-none-eabihf Ferrocene target provides support for bare-metal ARMv7-R processors with the ARM ISA, using the hard-float ABI with a double-precision capable FPU. This includes the Arm Cortex-R4, Cortex-R5, Cortex-R7 and Cortex-R8 with FPU architecture VFPv3-D16.

On this target, functions accepting f32 or f64 will have those arguments passed via FPU registers. For more information on the differences between the hard-float and soft-float ABIs, see the rustc book.

13.1. Prerequisites¶

This target has no pre-requisites.

13.2. Archives to install¶

The following archives are needed when installing this target as a cross-compilation target:

rust-std-armv7r-none-eabihf

13.3. Required compiler flags¶

To use the target, the following additional flags must be provided to rustc:

--target=armv7r-none-eabihf

13.4. Testing Facade (Experimental)¶

Bare metal targets cannot use test harnesses that require libc. Instead, a testing facade that emulates the bare metal target can be used instead, but also provides access to std functionality.

The following additional archive is needed when installing:

rust-std-armv7r-ferrocene.facade-eabihf

This target is the same as the one it proxies, except it includes a Linux libc, which means it can use std for testing and enriched interactive development on a Armv8-A Linux (glibc) or x86-64 Linux (glibc) host.

For more information, consult Testing Facades.